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Science-Related Homework Help Electrical Engineering Topic started by: neonfayt on Jan 23, 2018



Title: A blown input to an AND gate in a PLD would normally be held:
Post by: neonfayt on Jan 23, 2018
A blown input to an AND gate in a PLD would normally be held:
 
  A) HIGH. B) invalid. C) LOW. D) tri-state.


Title: A blown input to an AND gate in a PLD would normally be held:
Post by: icysparkles on Jan 23, 2018
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