1. The superscalar approach can be used on __________ architecture.
A. RISC B. CISC
C. neither RISC nor CISC D. both RISC and CISC
2. The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.
A. scalar B. branch
C. superscalar D. flow dependency
3. Which of the following is a fundamental limitation to parallelism with which the system must cope?
A. procedural dependency B. resource conflicts
C. antidependency D. all of the above
4. The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________.
A. true data dependency B. output dependency
C. procedural dependency D. antidependency
5. The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.
A. resource dependency B. procedural dependency
C. output dependency D. true data dependency
6. ________ refers to the process of initiating instruction execution in the processor’s functional units.
A. Instruction issue B. In-order issue
C. Out-of-order issue D. Procedural issue
7. Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses.
A. in-order issue B. resource conflict
C. antidependency D. out-of-order completion
8. ________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed execution and is ready for retirement.
A. State B. Memory address
C. Micro-op D. Alias register
9. __________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.
A. Flow dependency B. Instruction-level parallelism
C. Machine parallelism D. Instruction issue
10. _________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.
A. Machine parallelism B. Instruction-level parallelism
C. Output dependency D. Procedural dependency
11. ________ is a protocol used to issue instructions.
A. Micro-ops B. Scalar
C. SIMD D. Instruction issue policy
12. ________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles.
A. In-order completion B. In-order issue
C. Out-of-order completion D. Out-of-order issue
13. Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?
A. duplication of resources B. out-of-order issue
C. renaming D. all of the above
14. The ________ introduced a full-blown superscalar design with out-of-order execution.
A. Pentium B. Pentium Pro
C. 386 D. 486
15. Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions.
A. 486 B. Pentium
C. Intel Core D. Pentium Pro
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